1529 search results - page 45 / 306 » On Timing Analysis of Combinational Circuits |
ASPDAC
2007
ACM
15 years 3 months ago
2007
ACM
The scaling of CMOS technology into the nanometer era enables the fabrication of highly integrated systems, which increasingly contain analog and/or RF parts. However, scaling into...
100
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SAC
2006
ACM
15 years 5 months ago
2006
ACM
: In chip design, one of the main objectives is to decrease its clock cycle; however, the existing approaches to timing analysis under uncertainty are based on fundamentally restri...
101
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DATE
2010
IEEE
15 years 5 months ago
2010
IEEE
—With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits...
VLSID
2002
IEEE
16 years 6 days ago
2002
IEEE
Our target is automation of analog circuit's layout, which is a bottleneck in mixed-signal's design. We formulate the layout explicitly considering manufacturing process...
ICCAD
1997
IEEE
15 years 4 months ago
1997
IEEE
The circuit tuning problem is best approached by means of gradient-based nonlinear optimization algorithms. For large circuits, gradient computation can be the bottleneck in the o...