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» On Timing Analysis of Combinational Circuits
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PATMOS
2004
Springer
15 years 3 months ago
Leakage Power Analysis and Comparison of Deep Submicron Logic Gates
Basic combinational gates, including NAND, NOR and XOR, are fundamental building blocks in CMOS digital circuits. This paper analyses and compares the power consumption due to tran...
Geoff V. Merrett, Bashir M. Al-Hashimi
BMCBI
2008
178views more  BMCBI 2008»
14 years 9 months ago
A discriminative method for protein remote homology detection and fold recognition combining Top-n-grams and latent semantic ana
Background: Protein remote homology detection and fold recognition are central problems in bioinformatics. Currently, discriminative methods based on support vector machine (SVM) ...
Bin Liu, Xiaolong Wang, Lei Lin, Qiwen Dong, Xuan ...
SAC
2004
ACM
15 years 3 months ago
Combining analysis and synthesis in a model of a biological cell
for ideas, and then abstract away from these ideas to produce algorithmic processes that can create problem solutions in a bottom-up manner. We have previously described a top-dow...
Ken Webb, Tony White
ICCAD
2005
IEEE
176views Hardware» more  ICCAD 2005»
15 years 6 months ago
Statistical gate sizing for timing yield optimization
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
Debjit Sinha, Narendra V. Shenoy, Hai Zhou
ICCAD
2002
IEEE
107views Hardware» more  ICCAD 2002»
15 years 6 months ago
Theoretical and practical validation of combined BEM/FEM substrate resistance modeling
In mixed-signal designs, substrate noise originating from the digital part can seriously influence the functionality of the analog part. As such, accurately modeling the properti...
Eelco Schrik, Patrick Dewilde, N. P. van der Meijs