1529 search results - page 49 / 306 » On Timing Analysis of Combinational Circuits |
CORR
2010
Springer
14 years 9 months ago
2010
Springer
In this paper a new solution is proposed for testing simple stwo stage electronic circuits. It minimizes the number of tests to be performed to determine the genuinity of the circ...
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COCO
2011
Springer
13 years 9 months ago
2011
Springer
The class ACC consists of circuit families with constant depth over unbounded fan-in AND, OR, NOT, and MODm gates, where m > 1 is an arbitrary constant. We prove: • NTIME[2n ...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
In this paper, a wavelet based approach is proposed for the model order reduction of linear circuits in time domain. Compared with Chebyshev reduction method, the wavelet reductio...
CLEF
2008
Springer
14 years 11 months ago
2008
Springer
Abstract. LogAnswer is a logic-oriented question answering system developed by the AI research group at the University of Koblenz-Landau and by the IICS at the University of Hagen....
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...