1529 search results - page 51 / 306 » On Timing Analysis of Combinational Circuits |
DAC
2008
ACM
15 years 10 months ago
2008
ACM
This paper introduces an accurate and efficient electrical analysis of logic gates modeled as Multiple Voltage Threshold Models (MVTM) loaded by the associated interconnect. MVTMs...
ICCAD
2007
IEEE
15 years 4 months ago
2007
IEEE
Modeling the effect of coupling noise on circuit delay is a key issue in static timing analysis (STA) and involves the “victimaggressor alignment” problem. As delay-noise depe...
115
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ASPDAC
2008
ACM
14 years 11 months ago
2008
ACM
In the nanometer manufacturing region, process variation causes significant uncertainty for circuit performance verification. Statistical static timing analysis (SSTA) is thus dev...
104
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DAC
2004
ACM
15 years 10 months ago
2004
ACM
CT An efficient statistical timing analysis algorithm that can handle arbitrary (spatial and structural) causes of delay correlation is described. The algorithm derives the entire ...
ICCD
2007
IEEE
15 years 4 months ago
2007
IEEE
A methodology for constructing circuit-level mismatch models and performing yield optimization is presented for CMOS analog circuits. The methodology combines statistical techniqu...