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» On Timing Analysis of Combinational Circuits
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ITC
1998
IEEE
120views Hardware» more  ITC 1998»
15 years 2 months ago
Test generation in VLSI circuits for crosstalk noise
This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital c...
Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer
PR
2006
99views more  PR 2006»
14 years 9 months ago
Class-dependent PCA, MDC and LDA: A combined classifier for pattern classification
Several pattern classifiers give high classification accuracy but their storage requirements and processing time are severely expensive. On the other hand, some classifiers requir...
Alok Sharma, Kuldip K. Paliwal, Godfrey C. Onwubol...
DATE
2003
IEEE
101views Hardware» more  DATE 2003»
15 years 3 months ago
Combined FDTD/Macromodel Simulation of Interconnected Digital Devices
Behavioral models of digital devices based on Radial Basis Functions (RBF) are incorporated into a Finite-Difference Time-Domain (FDTD) solver for full-wave analysis of interconne...
Stefano Grivet-Talocia, Igor S. Stievano, Ivan A. ...
ICCD
2008
IEEE
121views Hardware» more  ICCD 2008»
15 years 6 months ago
Characterization and design of sequential circuit elements to combat soft error
- This paper performs analysis and design of latches and flip-flops while considering the effect of event upsets caused by energetic particle hits. First it is shown that the conve...
Hamed Abrishami, Safar Hatami, Massoud Pedram
ENGL
2007
118views more  ENGL 2007»
14 years 9 months ago
Design of Low Power CMOS Crystal Oscillator with Tuning Capacitors
—A low power CMOS crystal oscillator was proposed with high accuracy by tuning capacitors. Based on the analysis concerning power consumption, start-up time, and frequency stabil...
Shun Yao, Hengfang Zhu, Xiaobo Wu