1529 search results - page 57 / 306 » On Timing Analysis of Combinational Circuits |
ITC
2003
IEEE
15 years 3 months ago
2003
IEEE
A delay-locked loop (DLL) based built-in self test (BIST) circuit has been designed with a 0.18 µ m TSMC process (CM018) to test chip I/O speeds, specifically, the setup and hold...
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
— The paper introduces novel field programmable gate array (FPGA) circuits based on hybrid CMOS/resistive switching device (memristor) technology and explores several logic archi...
DATE
1999
IEEE
15 years 2 months ago
1999
IEEE
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
VLSID
1999
IEEE
15 years 2 months ago
1999
IEEE
To minimize the time to market and cost of new sub 0.25um process technologies and products, PDF Solutions, Inc., has developed a new comprehensive approach based on the use of pr...
ICCAD
2002
IEEE
15 years 6 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...