1529 search results - page 58 / 306 » On Timing Analysis of Combinational Circuits |
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ISCAS
2003
IEEE
15 years 3 months ago
2003
IEEE
We present an equation-based transistor size optimizer that minimizes delay of custom circuits. Our method uses static timing analysis to find the critical paths and numerical met...
ICTAI
2002
IEEE
15 years 2 months ago
2002
IEEE
In order to reduce the time-to-market and simplify gatelevel test generation for digital integrated circuits, GAbased functional test generation techniques are proposed for behavi...
DAC
2011
ACM
13 years 9 months ago
2011
ACM
This paper studies TSV-to-TSV coupling in 3D ICs. A full-chip SI analysis flow is proposed based on the proposed coupling model. Analysis results show that TSVs cause significan...
ISCAS
2002
IEEE
15 years 2 months ago
2002
IEEE
A novel charge-based comparator and folding circuit are presented. Correlated double sampling comparison is performed using a log-domain integrator, implemented by a subthreshold ...
EURODAC
1994
IEEE
15 years 1 months ago
1994
IEEE
Symbolic state space exploration techniques for Finite State Machines (FSMs) are a major recent result in CAD for VLSI. Most of them are exact and based on forward traversal, but ...