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» On Timing Analysis of Combinational Circuits
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ISCAS
2005
IEEE
126views Hardware» more  ISCAS 2005»
15 years 3 months ago
Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits
—Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits is presented in this paper. Noise immunity is enhanced by conditionally turning on the conditional k...
Chung-Hsien Hua, Wei Hwang, Chih-Kai Chen
ANSS
2000
IEEE
15 years 2 months ago
Multi-Resolution Modeling of Power Converter Using Waveform Reconstruction
Computer simulation of switching power converters is complicated by the discontinuous (switching) nature of the converter waveforms. When switching details of the waveforms are of...
Yuwei Luo, Roger Dougal, Enrico Santi
GLVLSI
2005
IEEE
99views VLSI» more  GLVLSI 2005»
15 years 3 months ago
An empirical study of crosstalk in VDSM technologies
We perform a detailed study of various crosstalk scenarios in VDSM technologies by using a distributed model of the crosstalk site and make a number of key observations about the ...
Shahin Nazarian, Massoud Pedram, Emre Tuncer
MSE
1999
IEEE
204views Hardware» more  MSE 1999»
15 years 2 months ago
A PC-based Educational Tool for CMOS Integrated Circuit Design
This paper presents a PC based software running on PC dedicated to the training in sub-micron CMOS VLSI design. The software firstly consists in a HDL-based schematic editor with ...
Etienne Sicard, Chen Xi
DAC
1998
ACM
15 years 10 months ago
A Mixed Nodal-Mesh Formulation for Efficient Extraction and Passive Reduced-Order Modeling of 3D Interconnects
As VLSI circuit speeds have increased, reliable chip and system design can no longer be performed without accurate threedimensional interconnect models. In this paper, we describe...
Nuno Alexandre Marques, Mattan Kamon, Jacob White,...