1529 search results - page 62 / 306 » On Timing Analysis of Combinational Circuits |
FPGA
2007
ACM
15 years 3 months ago
2007
ACM
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
TVLSI
2010
14 years 4 months ago
2010
To efficiently analyze the large-scale interconnect dominant circuits with inductive couplings (mutual inductances), this paper introduces a new state matrix, called VNA, to stamp ...
TVLSI
2008
14 years 9 months ago
2008
Applications in computer networks often require high throughput access to large data structures for lookup and classification. While advanced algorithms exist to speed these search...
ICCAD
1999
IEEE
15 years 2 months ago
1999
IEEE
This paper proposes a new bipatition-codec architecture that may reduce power consumption of pipelined circuits. We treat each output value of a pipelined circuit as one state of ...
ICCAD
1997
IEEE
15 years 2 months ago
1997
IEEE
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...