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» On Timing Analysis of Combinational Circuits
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CDES
2006
136views Hardware» more  CDES 2006»
14 years 11 months ago
CMOL FPGA circuits
Abstract--This paper describes an architecture of FPGAlike fabric for future hybrid "CMOL" circuits. Such circuits will combine a semiconductor-transistor (CMOS) stack an...
Dmitri B. Strukov, Konstantin Likharev
ICASSP
2008
IEEE
15 years 4 months ago
Nonnegative matrix factorization for real time musical analysis and sight-reading evaluation
Sight-reading is the ability to read and perform music from a written score with little or no preparation. Though an integral part of musicianship, it is rarely or minimally addre...
Chih-Chieh Cheng, D. Jingtong Hu, Lawrence K. Saul
ICCAD
1999
IEEE
66views Hardware» more  ICCAD 1999»
15 years 2 months ago
Timing-safe false path removal for combinational modules
A delay abstraction of a combinational module is a compact representation of the delay information of the module, which carries effective pin-to-pin delay for each primary-input/pr...
Yuji Kukimoto, Robert K. Brayton
ATS
2009
IEEE
92views Hardware» more  ATS 2009»
14 years 7 months ago
M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay
Negative bias temperature instability (NBTI) has been a significant reliability concern in current digital circuit design due to its effect of increasing the path delay with time a...
Song Jin, Yinhe Han, Lei Zhang 0008, Huawei Li, Xi...
DATE
2010
IEEE
180views Hardware» more  DATE 2010»
15 years 2 months ago
Reliability- and process variation-aware placement for FPGAs
Abstract—Negative bias temperature instability (NBTI) significantly affects nanoscale integrated circuit performance and reliability. The degradation in threshold voltage (Vth) d...
Assem A. M. Bsoul, Naraig Manjikian, Li Shang