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» On Timing Analysis of Combinational Circuits
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IPPS
2003
IEEE
15 years 3 months ago
SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems
With the current trend in integration of more complex systems on chip there is a need for better communication infrastructure on chip that will increase the available bandwidth an...
Daniel Wiklund, Dake Liu
DAC
2007
ACM
15 years 10 months ago
Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction
The ability to account for the growing impacts of multiple process variations in modern technologies is becoming an integral part of nanometer VLSI design. Under the context of ti...
Zhuo Feng, Peng Li, Yaping Zhan
DAC
2010
ACM
15 years 1 months ago
TSV stress aware timing analysis with applications to 3D-IC layout optimization
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee,...
IPPS
2005
IEEE
15 years 3 months ago
Dynamic RWA Based on the Combination of Mobile Agents Technique and Genetic Algorithm in WDM Networks with Sparse Wavelength Con
In this paper, we study the dynamic RWA problem in WDM networks with sparse wavelength conversion and propose a novel hybrid algorithm for it based on the combination of mobile ag...
Vinh Trong Le, Xiaohong Jiang, Son-Hong Ngo, Susum...
DAC
2005
ACM
15 years 10 months ago
Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions
While performance specifications are verified before sign-off for a modern nanometer scale design, extensive application of optical proximity correction substantially alters the l...
Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Denni...