1529 search results - page 72 / 306 » On Timing Analysis of Combinational Circuits |
DAC
2003
ACM
15 years 10 months ago
2003
ACM
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. This paper proposes a method of characterizing correlation of signal tra...
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FORMATS
2007
Springer
15 years 1 months ago
2007
Springer
Resource limited DRE (Distributed Real-time Embedded) systems can benefit greatly from dynamic adaptation of system parameters. We propose a novel approach that employs iterative t...
ISLPED
2009
ACM
15 years 2 months ago
2009
ACM
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...
UAI
1996
14 years 11 months ago
1996
Many algorithms for processing probabilistic networks are dependent on the topological properties of the problem's structure. Such algorithmse.g., clustering, conditioning ar...
TCAD
2002
14 years 9 months ago
2002
We develop a general methodology to analyze crosstalk effects that are likely to cause errors in deep submicron high speed circuits. We focus on crosstalk due to capacitive coupli...