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» On Timing Analysis of Combinational Circuits
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EOR
2007
92views more  EOR 2007»
14 years 9 months ago
Modelling profitability using survival combination scores
The paper presents the first empirical investigation of the relationship between present value of net revenue from a revolving credit account and times to default and to second pu...
Galina Andreeva, Jake Ansell, Jonathan Crook
GLVLSI
2003
IEEE
146views VLSI» more  GLVLSI 2003»
15 years 3 months ago
A practical CAD technique for reducing power/ground noise in DSM circuits
One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In...
Arindam Mukherjee, Krishna Reddy Dusety, Rajsaktis...
ASYNC
2000
IEEE
122views Hardware» more  ASYNC 2000»
15 years 2 months ago
DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen...
HPCC
2005
Springer
15 years 3 months ago
Lazy Home-Based Protocol: Combining Homeless and Home-Based Distributed Shared Memory Protocols
Abstract. This paper presents our novel protocol design and implementation of an all-software page-based DSM system. The protocol combines the advantages of homeless and home-based...
Byung-Hyun Yu, Paul Werstein, Martin K. Purvis, St...
HICSS
2002
IEEE
93views Biometrics» more  HICSS 2002»
15 years 2 months ago
A Combination Measurement for Studying Disorientation
The disorientation problem has been known to exist on hypertext and hypermedia systems. Various approaches have also been recommended and implemented in order to eliminate or redu...
Noor F. M. Yatim