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» On Timing Analysis of Combinational Circuits
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VTS
2003
IEEE
89views Hardware» more  VTS 2003»
15 years 3 months ago
Diagnosis of Delay Defects Using Statistical Timing Models
— In this paper, we study the problem of delay defect diagnosis based on statistical timing models. We propose a diagnosis algorithm that can effectively utilize statistical timi...
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-...
VLSID
2004
IEEE
147views VLSI» more  VLSID 2004»
15 years 10 months ago
Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
Shabbir H. Batterywala, Narendra V. Shenoy
DATE
2003
IEEE
120views Hardware» more  DATE 2003»
15 years 3 months ago
Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step
Abstract — This paper defines a new diagnosis problem for diagnosing delay defects based upon statistical timing models. We illustrate the differences between the delay defect d...
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-...
ITC
2000
IEEE
80views Hardware» more  ITC 2000»
15 years 2 months ago
A stand-alone integrated test core for time and frequency domain measurements
An area efficient and robust integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstructi...
Mohamed Hafed, Nazmy Abaskharoun, Gordon W. Robert...
ISCAS
2007
IEEE
114views Hardware» more  ISCAS 2007»
15 years 4 months ago
On the Suitability of Discrete-Time Receivers for Software-Defined Radio
—CMOS radio receiver architectures, based on radio frequency (RF) sampling followed by discrete-time (D-T) signal processing via switched-capacitor circuits, have recently been p...
Zhiyu Ru, Eric A. M. Klumperink, Bram Nauta