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» On Timing Analysis of Combinational Circuits
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ITC
2003
IEEE
177views Hardware» more  ITC 2003»
15 years 3 months ago
Analyzing the Effectiveness of Multiple-Detect Test Sets
Multiple-detect test sets have been shown to be effective in lowering defect level. Other researchers have noted that observing the effects of a defect can be controlled by sensit...
R. D. (Shawn) Blanton, Kumar N. Dwarakanath, Aniru...
WCET
2010
14 years 7 months ago
METAMOC: Modular Execution Time Analysis using Model Checking
Safe and tight worst-case execution times (WCETs) are important when scheduling hard realtime systems. This paper presents METAMOC, a modular method, based on model checking and s...
Andreas E. Dalsgaard, Mads Chr. Olesen, Martin Tof...
WSC
2007
15 years 4 days ago
Measuring manufacturing throughput using takt time analysis and simulation
This paper is motivated by a case study performed at a company that manufactures two main types of customized products. In an effort to significantly increase their throughput cap...
Jun Duanmu, Kevin Taaffe
DAC
2007
ACM
15 years 10 months ago
Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement
Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability challenges in nano-scale technology. This paper presents an efficient technique to characte...
Kunhyuk Kang, Kee-Jong Kim, Ahmad E. Islam, Muhamm...
WCET
2007
14 years 11 months ago
Finding DU-Paths for Testing of Multi-Tasking Real-Time Systems using WCET Analysis
Memory corruption is one of the most common software failures. For sequential software and multitasking software with synchronized data accesses, it has been shown that program fa...
Daniel Sundmark, Anders Pettersson, Christer Sandb...