1529 search results - page 88 / 306 » On Timing Analysis of Combinational Circuits |
TCAD
2010
14 years 8 months ago
2010
—With the scaling of complementary metal–oxide– semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacit...
ISQED
2008
IEEE
15 years 4 months ago
2008
IEEE
An efficient frequency-based clock analysis method: CSAV is proposed in this paper. It computes the circuit response by first solving the state equation in frequency domain, and...
ISQED
2008
IEEE
15 years 4 months ago
2008
IEEE
This paper presents a statistic-based approach for evaluating the testability of nodes in combinational circuits. This testability measurement is obtained via Monte Carlo simulati...
VLSID
2005
IEEE
15 years 10 months ago
2005
IEEE
Timing margin (slack) needs to be carefully managed to ensure a satisfactory timing yield. We propose a new design flow that combines a false-path-aware gate sizing and a statisti...
ECAI
2000
Springer
15 years 2 months ago
2000
Springer
AutoSteve performs automated electrical design based on qualitative simulation and functional abstraction. It is the first commercial product capable of performing these tasks for ...