1529 search results - page 8 / 306 » On Timing Analysis of Combinational Circuits |
ISQED
2009
IEEE
15 years 4 months ago
2009
IEEE
A system-level statistical analysis methodology is described that captures the impact of inter- and intra-die process variations for read timing failures in SRAM circuit blocks. U...
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DATE
1999
IEEE
15 years 1 months ago
1999
IEEE
Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation, It finds application in test pattern generation, delay-fault testing, combinational equivalen...
DATE
2003
IEEE
15 years 2 months ago
2003
IEEE
The architectural study of wireless communication systems typically requires simulations with high-level models for different analog and RF blocks. Among these blocks, frequency-t...
ICCAD
2000
IEEE
15 years 1 months ago
2000
IEEE
ct Static timing analysis has traditionally used the PERT method for identifying the critical path of a digital circuit. Due to the influence of the slope of a signal at a particul...
ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
—As process variations become a significant problem in deep sub-micron technology, a shift from deterministic static timing analysis to statistical static timing analysis for hig...