1529 search results - page 90 / 306 » On Timing Analysis of Combinational Circuits |
EMSOFT
2004
Springer
15 years 3 months ago
2004
Springer
We present a technique to approximate the worst-case execution time that combines structural analysis with a loop-bounding algorithm based on local induction variable analysis. St...
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
— Process variations in digital circuits make sequential circuit timing validation an extremely challenging task. In this paper, a Statistical Bellman-Ford (SBF) algorithm is pro...
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ECRTS
2007
IEEE
15 years 4 months ago
2007
IEEE
Of late, there has been a considerable interest in models, algorithms and methodologies specifically targeted towards designing hardware and software for streaming applications. ...
ASYNC
2010
IEEE
14 years 1 months ago
2010
IEEE
— Synchronizers play a key role in multi-clock domain systems on chip. Traditionally, improvement of synchronization parameters with scaling has been assumed. In particular, the ...
TVLSI
2008
14 years 9 months ago
2008
To satisfy the advanced forward-error-correction (FEC) standards, in which the Convolutional code and Turbo code may co-exit, a prototype design of a unified Convolutional/Turbo de...