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» On Timing Analysis of Combinational Circuits
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VTS
2000
IEEE
114views Hardware» more  VTS 2000»
15 years 2 months ago
Detection of CMOS Defects under Variable Processing Conditions
Transient Signal Analysis is a digital device testing method that is based on the analysis of voltage transients at multiple test points. In this paper, the power supply transient...
Amy Germida, James F. Plusquellic
DAC
2001
ACM
15 years 10 months ago
Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping
In this paper, we study the problem of performance-driven multi-level circuit clustering with application to hierarchical FPGA designs. We first show that the performance-driven m...
Jason Cong, Michail Romesis
BROADNETS
2006
IEEE
15 years 3 months ago
SLIP-IN Architecture: A new Hybrid Optical Switching Scheme
— In this paper, we present a new hybrid switching architecture, termed as SLIP-IN, that combines electronic packet/burst with optical circuit switching. SLIP-IN architecture tak...
Kostas Ramantas, Kostas Christodoulopoulos, Kyriak...
FPL
2007
Springer
105views Hardware» more  FPL 2007»
15 years 4 months ago
Time Predictable CPU and DMA Shared Memory Access
In this paper, we propose a first step towards a time predictable computer architecture for single-chip multiprocessing (CMP). CMP is the actual trend in server and desktop syste...
Christof Pitter, Martin Schoeberl
RTS
2006
129views more  RTS 2006»
14 years 9 months ago
Modeling out-of-order processors for WCET analysis
Estimating the Worst Case Execution Time (WCET) of a program on a given processor is important for the schedulability analysis of real-time systems. WCET analysis techniques typic...
Xianfeng Li, Abhik Roychoudhury, Tulika Mitra