1529 search results - page 96 / 306 » On Timing Analysis of Combinational Circuits |
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IEEEPACT
2009
IEEE
14 years 7 months ago
2009
IEEE
Transactional memory is being advanced as an alternative to traditional lock-based synchronization for concurrent programming. Transactional memory simplifies the programming mode...
ITC
2003
IEEE
15 years 3 months ago
2003
IEEE
This paper describes a new post-silicon validation problem for diagnosing systematic timing errors. We illustrate the differences between timing validation and the traditional log...
RSP
2003
IEEE
15 years 3 months ago
2003
IEEE
This paper addresses the need for systematic verification of timing properties of real-time prototypes, which consist of timing constraints that must be satisfied at any given tim...
TVLSI
2008
14 years 9 months ago
2008
With aggressive scaling down of feature sizes in VLSI fabrication, process variation has become a critical issue in designs. We show that two necessary conditions for the "Max...
TODAES
2002
14 years 9 months ago
2002
ct Cross-coupled noise analysis has become a critical concern in today's VLSI designs. Typically, noise analysis makes an assumption that all aggressing nets can simultaneousl...