1529 search results - page 99 / 306 » On Timing Analysis of Combinational Circuits |
DAC
2003
ACM
15 years 10 months ago
2003
ACM
This paper presents a power grid analyzer based on a random walk technique. A linear-time algorithm is first demonstrated for DC analysis, and is then extended to perform transien...
DAC
1994
ACM
15 years 2 months ago
1994
ACM
In current research, the minimum cycle times of finite state machines are estimated by computing the delays of the combinational logic in the finite state machines. Even though th...
CCGRID
2009
IEEE
15 years 4 months ago
2009
IEEE
Highly distributed systems such as Grids are used today to the execution of large-scale parallel applications. The behavior analysis of these applications is not trivial. The comp...
DATE
2007
IEEE
15 years 4 months ago
2007
IEEE
This paper presents a built-in self-test (BiST) scheme for analog to digital converters (ADC) based on a linear ramp generator and efficient output analysis. The proposed analysi...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
Test sets that detect each target fault n times (n-detection test sets) are typically generated for restricted values of n due to the increase in test set size with n. We perform ...