1529 search results - page 9 / 306 » On Timing Analysis of Combinational Circuits |
DAC
2002
ACM
15 years 10 months ago
2002
ACM
We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool ...
ATS
2000
IEEE
15 years 2 months ago
2000
IEEE
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
A new algorithm is presented that combines performance and variation objectives in a behavioural model for a given analogue circuit topology and process. The tradeoffs between per...
DAC
1999
ACM
15 years 1 months ago
1999
ACM
As interconnect feature sizes continue to scale to smaller dimensions, long interconnect can dominate the IC timing performance, but the interconnect parameter variations make it ...
ASPDAC
2004
ACM
15 years 3 months ago
2004
ACM
Abstract— This paper presents a power grid analyzer that combines a divide-and-conquer strategy with a random-walk engine. A single-level hierarchical method is first described ...