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» On Tool Integration in High-Performance FPGA Design Flows
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ICCAD
2007
IEEE
157views Hardware» more  ICCAD 2007»
15 years 6 months ago
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture
—In this paper, we introduce a novel reconfigurable architecture, named 3D nFPGA, which utilizes 3D integration techniques and new nanoscale materials synergistically. The propos...
Chen Dong, Deming Chen, Sansiri Tanachutiwat, Wei ...
FPL
2004
Springer
90views Hardware» more  FPL 2004»
15 years 3 months ago
Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis
Abstract. Layout tools for FPGAs can typically be run in two different modes: non-timing-driven and timing-driven. Non-timing-driven mode produces a solution quickly, without consi...
Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, ...
SASP
2009
IEEE
291views Hardware» more  SASP 2009»
15 years 4 months ago
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs
— As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore’s law, the computing industry has switched its route...
Alexandros Papakonstantinou, Karthik Gururaj, John...
DAC
2004
ACM
15 years 10 months ago
FPGA power reduction using configurable dual-Vdd
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
Fei Li, Yan Lin, Lei He
DATE
2008
IEEE
163views Hardware» more  DATE 2008»
15 years 4 months ago
Design flow for embedded FPGAs based on a flexible architecture template
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many appl...
B. Neumann, Thorsten von Sydow, Holger Blume, Tobi...