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» On Tool Integration in High-Performance FPGA Design Flows
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CHES
2009
Springer
150views Cryptology» more  CHES 2009»
15 years 4 months ago
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been p...
Francesco Regazzoni, Alessandro Cevrero, Fran&cced...
FPGA
2010
ACM
250views FPGA» more  FPGA 2010»
15 years 6 months ago
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
Gregory Lucas, Chen Dong, Deming Chen
FDL
2005
IEEE
15 years 3 months ago
Integrating Model-Checking with UML-based SoC Development
In order to address the complexities of SoC design, rigorous development methods and automated tools are required. This paper presents an approach to formal verification using mod...
Peter Green, Kinika Tasie-Amadi
MSE
2005
IEEE
137views Hardware» more  MSE 2005»
15 years 3 months ago
Teaching SoC Design in a Project-Oriented Course Based on Robotics
The fast growing complexity and short time-tomarket of embedded systems designs, besides the great increase in capacity of today’s chips, are mobilizing the industry towards to ...
Abner Correa Barros, Pericles Lima, Juliana Xavier...
DAC
2008
ACM
14 years 11 months ago
Programmable logic circuits based on ambipolar CNFET
Recently, it was demonstrated that the polarity of carbon nanotube field effect transistors can be electrically controlled. In this paper we show how Programmable Logic Arrays (PL...
M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebic...