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» On Tool Integration in High-Performance FPGA Design Flows
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FCCM
2011
IEEE
331views VLSI» more  FCCM 2011»
14 years 1 months ago
Synthesis of Platform Architectures from OpenCL Programs
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
Muhsen Owaida, Nikolaos Bellas, Konstantis Dalouka...
RSP
2003
IEEE
176views Control Systems» more  RSP 2003»
15 years 2 months ago
Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment
This paper describes the early analysis and estimation features currently implemented in the Berkeley Emulation Engine (BEE) system. BEE is an integrated rapid prototyping and des...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, A...
FPL
2000
Springer
128views Hardware» more  FPL 2000»
15 years 1 months ago
Verification of Dynamically Reconfigurable Logic
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...
David Robinson, Patrick Lysaght
ASPDAC
2006
ACM
148views Hardware» more  ASPDAC 2006»
15 years 3 months ago
An automated design flow for 3D microarchitecture evaluation
- Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact...
Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Re...
DATE
2009
IEEE
150views Hardware» more  DATE 2009»
15 years 4 months ago
A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs
—Interconnect structures significantly contribute to the delay, power consumption, and silicon area of modern reconfigurable architectures. The demand for higher clock frequencie...
Kostas Siozios, Vasilis F. Pavlidis, Dimitrios Sou...