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    DAC
    2004
    ACM
    146views Computer Architecture» more  DAC 2004»
    An analytical approach for dynamic range estimation
    15 years 11 months ago
    An analytical approach for dynamic range estimation
    Download  www.eecg.toronto.edu
    It has been widely recognized that the dynamic range information of an application can be exploited to reduce the datapath bitwidth of either processors or ASICs, and therefore th...
    Bin Wu, Jianwen Zhu, Farid N. Najm
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    DAC
    2005
    ACM
    109views Computer Architecture» more  DAC 2005»
    Device and architecture co-optimization for FPGA power reduction
    15 years 11 months ago
    Device and architecture co-optimization for FPGA power reduction
    Download  www.ee.ucla.edu
    Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
    Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
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    DAC
    2005
    ACM
    167views Computer Architecture» more  DAC 2005»
    Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions
    15 years 11 months ago
    Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions
    Download  www.cs.york.ac.uk
    While performance specifications are verified before sign-off for a modern nanometer scale design, extensive application of optical proximity correction substantially alters the l...
    Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Denni...
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    DAC
    2005
    ACM
    134views Computer Architecture» more  DAC 2005»
    Robust gate sizing by geometric programming
    15 years 11 months ago
    Robust gate sizing by geometric programming
    Download  www.ece.umn.edu
    We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
    Jaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, ...
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    DAC
    2006
    ACM
    141views Computer Architecture» more  DAC 2006»
    Timing-based delay test for screening small delay defects
    15 years 11 months ago
    Timing-based delay test for screening small delay defects
    Download  www.engr.uconn.edu
    The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...
    Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
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