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» On Using Efficient Test Sequences for BIST
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DELTA
2004
IEEE
15 years 5 months ago
Scan Test of IP Cores in an ATE Environment
Manufacturing test of chips made of multiple IP cores requires different techniques if ATE is used. As scan chains are commonly used as access paths to the DUT, ATE architectures ...
Luca Schiano, Yong-Bin Kim, Fabrizio Lombardi
CVPR
2003
IEEE
16 years 3 months ago
Subset Selection for Efficient SVM Tracking
We update the SVM score of an object through a video sequence with a small and variable subset of support vectors. In the first frame we use all the support vectors to compute the...
Shai Avidan
SNPD
2008
15 years 3 months ago
Testing Component-Based Real Time Systems
This paper focuses on studying efficient solutions for modeling and deriving compositional tests for component-based real-time systems. In this work, we propose a coherent framewo...
Rachid Bouaziz, Ismail Berrada
139
Voted
BMCBI
2006
115views more  BMCBI 2006»
15 years 1 months ago
The accuracy of several multiple sequence alignment programs for proteins
Background: There have been many algorithms and software programs implemented for the inference of multiple sequence alignments of protein and DNA sequences. The "true" ...
Paulo A. S. Nuin, Zhouzhi Wang, Elisabeth R. M. Ti...
121
Voted
DAC
2000
ACM
16 years 2 months ago
Self-test methodology for at-speed test of crosstalk in chip interconnects
The effect of crosstalk errors is most significant in highperformance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that...
Xiaoliang Bai, Sujit Dey, Janusz Rajski