187 search results - page 4 / 38 » On Using Efficient Test Sequences for BIST |
VTS
2000
IEEE
13 years 10 months ago
2000
IEEE
We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence gen...
ITC
1996
IEEE
13 years 10 months ago
1996
IEEE
Abstract. In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not comp...
DELTA
2008
IEEE
14 years 22 days ago
2008
IEEE
Re-using embedded resources for implementing builtin self test mechanisms allows test cost reduction. In this paper we demonstrate how to implement costefficient built-in self tes...
ITC
1996
IEEE
13 years 10 months ago
1996
IEEE
This paper presents a low-overhead scheme for built-in self-test of circuits with scan. Complete (100%) fault coverage is obtained without modifying the function logic and without...
ISQED
2002
IEEE
13 years 11 months ago
2002
IEEE
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...