187 search results - page 7 / 38 » On Using Efficient Test Sequences for BIST |
DSD
2005
IEEE
14 years 11 months ago
2005
IEEE
Several methods improving the fault coverage in mixed-mode BIST are presented in this paper. The test is divided into two phases: the pseudo-random and deterministic. Maximum of f...
70
Voted
FPL
2004
Springer
15 years 2 months ago
2004
Springer
This paper presents a novel approach to interconnect fault location for FPGAs during power-on sequence. The method is based on a concept known as fault grading which utilizes defec...
GLVLSI
2003
IEEE
15 years 2 months ago
2003
IEEE
In this paper a novel reseeding architecture for scan-based BIST, which uses an LFSR as TPG, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan c...
65
Voted
VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
This paper considers reducing the cost of test application by permuting test vectors to improve their defect coverage. Algorithms for test reordering are developed with the goal o...
BMCBI
2005
14 years 9 months ago
2005
Background: Most current DNA diagnostic tests for identifying organisms use specific oligonucleotide probes that are complementary in sequence to, and hence only hybridise with th...