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» On Using Efficient Test Sequences for BIST
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ICCAD
1994
IEEE
76views Hardware» more  ICCAD 1994»
15 years 1 months ago
An efficient procedure for the synthesis of fast self-testable controller structures
The BIST implementation of a conventionally synthesized controller in most cases requires the integration of an additional register only for test purposes. This leads to some seri...
Sybille Hellebrand, Hans-Joachim Wunderlich
DSD
2005
IEEE
75views Hardware» more  DSD 2005»
15 years 3 months ago
An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform
We describe a new e-learning environment and a runtime platform for educational tools on digital system testing and design for testability. This environment is being developed in ...
Artur Jutman, Jaan Raik, Raimund Ubar, V. Vislogub...
ICSE
2005
IEEE-ACM
15 years 9 months ago
Efficient and precise dynamic impact analysis using execute-after sequences
As software evolves, impact analysis estimates the potential effects of changes, before or after they are made, by identifying which parts of the software may be affected by such ...
Taweesup Apiwattanapong, Alessandro Orso, Mary Jea...
DATE
2008
IEEE
126views Hardware» more  DATE 2008»
14 years 11 months ago
State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores
1 We present a new type of Linear Feedback Shift Registers, State Skip LFSRs. State Skip LFSRs are normal LFSRs with the addition of a small linear circuit, the State Skip circuit,...
V. Tenentes, Xrysovalantis Kavousianos, Emmanouil ...
DATE
2006
IEEE
134views Hardware» more  DATE 2006»
15 years 3 months ago
Power constrained and defect-probability driven SoC test scheduling with test set partitioning
1 This paper presents a test scheduling approach for system-onchip production tests with peak-power constraints. An abort-onfirst-fail test approach is assumed, whereby the test is...
Zhiyuan He, Zebo Peng, Petru Eles