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» On bounding the delay of a critical path
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ARITH
2007
IEEE
15 years 6 months ago
Design of the ARM VFP11 Divide and Square Root Synthesisable Macrocell
This paper presents the detailed design of the ARM VFP11 Divide and Square Root synthesisable macrocell. The macrocell was designed using the minimum-redundancy radix-4 SRT digit ...
Neil Burgess, Chris N. Hinds
RTSS
2006
IEEE
15 years 5 months ago
Modeling and Worst-Case Dimensioning of Cluster-Tree Wireless Sensor Networks
Time-sensitive Wireless Sensor Network (WSN) applications require finite delay bounds in critical situations. This paper provides a methodology for the modeling and the worst-case...
Anis Koubaa, Mário Alves, Eduardo Tovar
DAC
1994
ACM
15 years 3 months ago
Exact Minimum Cycle Times for Finite State Machines
In current research, the minimum cycle times of finite state machines are estimated by computing the delays of the combinational logic in the finite state machines. Even though th...
William K. C. Lam, Robert K. Brayton, Alberto L. S...
NECO
2007
74views more  NECO 2007»
14 years 11 months ago
Phase Transition and Hysteresis in an Ensemble of Stochastic Spiking Neurons
An ensemble of stochastic non-leaky integrate-and-fire neurons with global, delayed and excitatory coupling and a small refractory period is analyzed. Simulations with adiabatic ...
Andreas Kaltenbrunner, Vicenç Gómez,...
ICCAD
2004
IEEE
127views Hardware» more  ICCAD 2004»
15 years 8 months ago
A yield improvement methodology using pre- and post-silicon statistical clock scheduling
— In deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. In this paper,...
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Pin...