This paper presents the detailed design of the ARM VFP11 Divide and Square Root synthesisable macrocell. The macrocell was designed using the minimum-redundancy radix-4 SRT digit ...
Time-sensitive Wireless Sensor Network (WSN) applications require finite delay bounds in critical situations. This paper provides a methodology for the modeling and the worst-case...
In current research, the minimum cycle times of finite state machines are estimated by computing the delays of the combinational logic in the finite state machines. Even though th...
William K. C. Lam, Robert K. Brayton, Alberto L. S...
An ensemble of stochastic non-leaky integrate-and-fire neurons with global, delayed and excitatory coupling and a small refractory period is analyzed. Simulations with adiabatic ...
— In deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. In this paper,...
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Pin...