301 search results - page 29 / 61 » On bounding the delay of a critical path |
DAC
2006
ACM
16 years 24 days ago
2006
ACM
In this paper, we propose a new linear programming based timing driven placement framework for high performance designs. Our LP framework is mainly net-based, but it takes advanta...
123
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ISCAS
2008
IEEE
15 years 6 months ago
2008
IEEE
— Reordered normal basis is a certain permutation of a type II optimal normal basis. In this paper, a high speed design of a word level finite field multiplier using reordered ...
FPT
2005
IEEE
15 years 5 months ago
2005
IEEE
A methodology for supporting dynamic voltage scaling (DVS) on commercial FPGAs is described. A logic delay measurement circuit (LDMC) is used to determine the speed of an inverter...
ISPD
1999
ACM
15 years 4 months ago
1999
ACM
- In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a path-based delay model to capture the timing c...
109
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ICCAD
2010
IEEE
14 years 9 months ago
2010
IEEE
For a variety of signal processing applications polynomials are implemented in circuits. Recent work on polynomial datapath optimization achieved significant reductions of hardware...