301 search results - page 30 / 61 » On bounding the delay of a critical path |
DAC
2012
ACM
13 years 2 months ago
2012
ACM
Near-threshold operation has emerged as a competitive approach for energy-efficient architecture design. In particular, a combination of near-threshold circuit techniques and par...
DAC
2000
ACM
16 years 24 days ago
2000
ACM
Custom design, in which the designer controls the physical structure of the chip, can greatly improve the speed, power, and delay of an ASIC chip without affecting design time. Th...
TON
2002
14 years 11 months ago
2002
In this paper we introduce and investigate a new" path optimization problem which we denote as the All Hops Optimal Path AHOP problem. The problem involves identifying, for a...
ISQED
2007
IEEE
15 years 6 months ago
2007
IEEE
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
DSD
2004
IEEE
15 years 3 months ago
2004
IEEE
In this paper, we present a full-static carry-skip adder designed to achieve low power dissipation and high-performance operation. To reduce the adder's delay and power consu...