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» On bounding the delay of a critical path
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ASPDAC
2005
ACM
100views Hardware» more  ASPDAC 2005»
15 years 1 months ago
Microarchitecture evaluation with floorplanning and interconnect pipelining
— As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple c...
Ashok Jagannathan, Hannah Honghua Yang, Kris Konig...
DAC
2003
ACM
15 years 5 months ago
Crosstalk noise in FPGAs
In recent years, due to rapid advances in VLSI manufacturing technology capable of packing more and more devices and wires on a chip, crosstalk has emerged as a serious problem af...
Yajun Ran, Malgorzata Marek-Sadowska
ICCAD
2005
IEEE
114views Hardware» more  ICCAD 2005»
15 years 8 months ago
Statistical timing analysis with two-sided constraints
Based on a timing yield model, a statistical static timing analysis technique is proposed. This technique preserves existing methodology by selecting a “device file setting” ...
Khaled R. Heloue, Farid N. Najm
ICCD
2001
IEEE
98views Hardware» more  ICCD 2001»
15 years 8 months ago
Design Alternatives for Parallel Saturating Multioperand Adders
Parallel saturating multioperand adders significantly improve the performance of GSM speech coders by giving compilers and assembly language programmers the ability to paralleliz...
Pablo I. Balzola, Michael J. Schulte, Jie Ruan, C....
ISLPED
2000
ACM
70views Hardware» more  ISLPED 2000»
15 years 4 months ago
An adaptive on-chip voltage regulation technique for low-power applications
In this paper we present a completely on-chip voltage regulation technique which promises to adjust the degree of voltage regulation in a digital logic chip in the face of process...
Nicola Dragone, Akshay Aggarwal, L. Richard Carley