301 search results - page 40 / 61 » On bounding the delay of a critical path |
HPCA
1999
IEEE
15 years 4 months ago
1999
IEEE
This work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/ execute decoupling and simultaneous multithreading. We investigate how b...
ICCAD
1990
IEEE
15 years 3 months ago
1990
IEEE
We present a hierarchicaltechniquefor floorplanning and pin assignment of the general cell layouts. Given a set of cells with their shape lists, a layout aspect ratio, relative po...
81
Voted
ASPDAC
2009
ACM
15 years 6 months ago
2009
ACM
Abstract— Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes...
DATE
2007
IEEE
15 years 6 months ago
2007
IEEE
—Increasing power density causes die overheating due to limited cooling capacity of the package. Conventional thermal management techniques e.g. logic shutdown, clock gating, fre...
ISQED
2006
IEEE
15 years 5 months ago
2006
IEEE
Gate-length biasing is a runtime leakage reduction technique that leverages on the short-channel effect by marginally increasing the gate-length of MOS devices to significantly ...