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» On bounding the delay of a critical path
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ISCA
1995
IEEE
120views Hardware» more  ISCA 1995»
15 years 3 months ago
Streamlining Data Cache Access with Fast Address Calculation
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
Todd M. Austin, Dionisios N. Pnevmatikatos, Gurind...
ICCCN
2007
IEEE
15 years 1 months ago
Greedy Face Routing with Face ID Support in Wireless Networks
—Geographic face routing provides an attractive way for packet delivery in wireless networks due to its high reliability and low overhead. A good face routing protocol should pro...
Shao Tao, Akkihebbal L. Ananda, Mun Choon Chan
78
Voted
DAC
2009
ACM
16 years 23 days ago
Timing-driven optimization using lookahead logic circuits
This paper describes a function-based timing-driven optimization technique for the synthesis of multi-level logic circuits. Motivated by the principles of parallel prefix computat...
Mihir R. Choudhury, Kartik Mohanram
ICCAD
2006
IEEE
169views Hardware» more  ICCAD 2006»
15 years 8 months ago
Microarchitecture parameter selection to optimize system performance under process variation
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...
Xiaoyao Liang, David Brooks
78
Voted
ICCAD
2003
IEEE
140views Hardware» more  ICCAD 2003»
15 years 8 months ago
Block-based Static Timing Analysis with Uncertainty
Static timing analysis is a critical step in design of any digital integrated circuit. Technology and design trends have led to significant increase in environmental and process v...
Anirudh Devgan, Chandramouli V. Kashyap