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» On bounding the delay of a critical path
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CODES
2000
IEEE
15 years 1 months ago
Program path analysis to bound cache-related preemption delay in preemptive real-time systems
ÍÒÔÖ Ø Ð Ú ÓÖ Ó Ñ ÑÓÖÝ Ñ × Ø Æ ÙÐØ ØÓ ר Ø ÐÐÝ Ò ÐÝÞ Ø ÛÓÖר¹ × Ô Ö ÓÖÑ Ò Ó Ö Ð¹Ø Ñ ×Ýר Ñ׺ Ì × ÔÖÓ Ð Ñ × Ü ...
Hiroyuki Tomiyama, Nikil D. Dutt
81
Voted
ITC
2000
IEEE
88views Hardware» more  ITC 2000»
15 years 1 months ago
Predicting device performance from pass/fail transient signal analysis data
Transient Signal Analysis (TSA) is a Go/No-Go device testing method that is based on the analysis of voltage transients at multiple test points. In this paper, a technique based o...
James F. Plusquellic, Amy Germida, Jonathan Hudson...
IJITWE
2010
118views more  IJITWE 2010»
14 years 6 months ago
Critical Path Based Approach for Predicting Temporal Exceptions in Resource Constrained Concurrent Workflows
Departmental workflows within a digital business ecosystem are often executed concurrently and required to share limited number of resources. However, unexpected events from the b...
Iok-Fai Leong, Yain-Whar Si, Robert P. Biuk-Aghai
102
Voted
ANSS
1991
IEEE
15 years 1 months ago
Supercritical speedup
The notions of the critical path of events and critical time of an event are key concepts in analyzing the performance of a parallel discrete event simulation. The highest critica...
David R. Jefferson, Peter L. Reiher
IOLTS
2005
IEEE
141views Hardware» more  IOLTS 2005»
15 years 3 months ago
A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning
With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spect...
Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy