301 search results - page 57 / 61 » On bounding the delay of a critical path |
84
Voted
SIPS
2006
IEEE
15 years 3 months ago
2006
IEEE
Abstract— This paper presents a design environment for efficiently generating application-specific Intellectual Property (IP) cores for system level signal processing algorithm...
77
Voted
ISPD
2003
ACM
15 years 2 months ago
2003
ACM
Floorplanning individual pipelined array modules of a larger overall die can yield beneficial results. Critical paths in every pipeline stage of a pipelined design are roughly equ...
FPGA
2001
ACM
15 years 2 months ago
2001
ACM
The routing architecture of an FPGA consists of the length of the wires, the type of switch used to connect wires (buffered, unbuffered, fast or slow) and the topology of the inte...
IEEEPACT
2000
IEEE
15 years 1 months ago
2000
IEEE
In this paper, we look at two issues which could affect the performance of value prediction on wide-issue ILP processors. One is the large number of accesses to the value predicti...
86
Voted
FPGA
1998
ACM
15 years 1 months ago
1998
ACM
Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing archit...