301 search results - page 6 / 61 » On bounding the delay of a critical path |
ICCAD
2002
IEEE
15 years 6 months ago
2002
IEEE
– In this paper we present multi-objective hMetis partitioning for simultaneous cutsize and circuit delay minimization. We change the partitioning process itself by introducing a...
TC
2008
14 years 9 months ago
2008
A novel serial-in parallel-out finite field multiplier using redundant representation is proposed. It is shown that the proposed architecture has either a significantly lower compl...
ISCAS
2003
IEEE
15 years 2 months ago
2003
IEEE
We present an equation-based transistor size optimizer that minimizes delay of custom circuits. Our method uses static timing analysis to find the critical paths and numerical met...
ASPDAC
2000
ACM
15 years 1 months ago
2000
ACM
We propose an efficient hardware architecture for the Blowfish algorithm [1]. The speed is up to 4 bit/clock, which is 9 times faster than a Pentium. By applying operator-reschedul...
CORR
2011
Springer
14 years 4 months ago
2011
Springer
We study how the choice of packet scheduling algorithms influences end-to-end performance on long network paths. Taking a network calculus approach, we consider both deterministi...