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» On bounding the delay of a critical path
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FPL
2007
Springer
98views Hardware» more  FPL 2007»
14 years 11 months ago
Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices
Reconfiguration time in dynamically-reconfigurable modular systems can severely limit application run-time compared to the critical path delay. In this paper we present a novel ...
Shannon Koh, Oliver Diessel
INFOCOM
2009
IEEE
15 years 4 months ago
Polynomial Time Approximations for Multi-Path Routing with Bandwidth and Delay Constraints
— In this paper, we study the problem of multi-path routing with bandwidth and delay constraints, which arises in applications for video delivery over bandwidth-limited networks....
Satyajayant Misra, Guoliang Xue, Dejun Yang
91
Voted
DAC
2004
ACM
15 years 10 months ago
Worst-case circuit delay taking into account power supply variations
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...
Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm
74
Voted
MST
2002
152views more  MST 2002»
14 years 9 months ago
Average-Case Analysis of Greedy Packet Scheduling
We study the average number of delays suffered by packets routed using greedy (work conserving) scheduling policies. We obtain tight bounds on the worst-case average number of del...
Zvi Lotker, Boaz Patt-Shamir
75
Voted
VLSISP
2008
145views more  VLSISP 2008»
14 years 9 months ago
Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box
Cryptographic substitution boxes (S-boxes) are an integral part of modern block ciphers like the Advanced Encryption Standard (AES). There exists a rich literature devoted to the ...
Stefan Tillich, Martin Feldhofer, Thomas Popp, Joh...