Sciweavers

2658 search results - page 262 / 532
» On efficient balanced codes
Sort
View
ISCA
2006
IEEE
131views Hardware» more  ISCA 2006»
16 years 8 days ago
Reducing Startup Time in Co-Designed Virtual Machines
A Co-Designed Virtual Machine allows designers to implement a processor via a combination of hardware and software. Dynamic binary translation converts code written for a conventi...
Shiliang Hu, James E. Smith
CODES
2002
IEEE
15 years 11 months ago
Communication speed selection for embedded systems with networked voltage-scalable processors
High-speed serial network interfaces are gaining wide use in connecting multiple processors and peripherals in modern embedded systems, thanks to their size advantage and power ef...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh
ICIP
2002
IEEE
15 years 11 months ago
An iterative algorithm for context selection in adaptive entropy coders
Context-based adaptive entropy coding is an essential feature of modern image compression algorithms; however, the design of these coders is non-trivial due to the balance that mu...
Tong Jin, Jacques Vaisey
HPCA
2000
IEEE
15 years 10 months ago
Dynamic Cluster Assignment Mechanisms
Clustered microarchitectures are an effective approach to reducing the penalties caused by wire delays inside a chip. Current superscalar processors have in fact a two-cluster mic...
Ramon Canal, Joan-Manuel Parcerisa, Antonio Gonz&a...
ISCC
2000
IEEE
15 years 10 months ago
Light Weight Security for Parallel Access to Multiple Mirror Sites
Mirror sites approach has been proposed recently for reducing the access delay and providing load balancing in network servers. In the mirror site approach a file, such as a multi...
Bülent Yener