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ARC
2010
Springer
183views Hardware» more  ARC 2010»
15 years 6 months ago
Integrated Design Environment for Reconfigurable HPC
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
Lilian Janin, Shoujie Li, Doug Edwards
128
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ECEASST
2006
96views more  ECEASST 2006»
15 years 6 months ago
Optimizing Pattern Matching Compilation by Program Transformation
Motivated by the promotion of rewriting techniques and their use in major industrial applications, we have designed Tom: a pattern matching layer on top of conventional programming...
Emilie Balland, Pierre-Etienne Moreau
CORR
2004
Springer
140views Education» more  CORR 2004»
15 years 6 months ago
Checking modes of HAL programs
Recent constraint logic programming (CLP) languages, such as HAL and Mercury, require type, mode and determinism declarations for predicates. This information allows the generatio...
Maria J. García de la Banda, Warwick Harvey...
CASES
2010
ACM
15 years 4 months ago
Mighty-morphing power-SIMD
In modern wireless devices, two broad classes of compute-intensive applications are common: those with high amounts of data-level parallelism, such as signal processing used in wi...
Ganesh S. Dasika, Mark Woh, Sangwon Seo, Nathan Cl...
150
Voted
ICPR
2010
IEEE
15 years 4 months ago
Cascaded Background Subtraction Using Block-Based and Pixel-Based Codebooks
This paper presents a cascaded scheme with block-based and pixel-based codebooks for background subtraction. The codebook is mainly used to compress information to achieve high ef...
Jing-Ming Guo, Chih-Sheng Hsu