Sciweavers

2658 search results - page 416 / 532
» On efficient balanced codes
Sort
View
IAJIT
2010
140views more  IAJIT 2010»
15 years 3 months ago
HW/SW Design-Based Implementation of Vector Median Rational Hybrid Filter
: A new code sign implementation of vector median rational hybrid filter based on efficient hardware/software implementation is introduced and applied to colour image filtering pro...
Anis Boudabous, Ahmed Ben Atitallah, Lazhar Khriji...
IJHPCA
2010
88views more  IJHPCA 2010»
15 years 3 months ago
Madre: the Memory-Aware Data Redistribution Engine
We report on the development of a new computational framework for efficiently carrying out parallel data redistribution in a limited memory environment. This new library, MADRE (T...
Stephen F. Siegel, Andrew R. Siegel
FPL
2010
Springer
267views Hardware» more  FPL 2010»
15 years 2 months ago
A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor
Due to the continuously decreasing cost of FPGAs, they have become a valid implementation platform for SOCs. Typically, a soft core processor implementation is used to execute the ...
Gerald Hempel, Christian Hochberger, Andreas Koch
160
Voted
GLOBECOM
2010
IEEE
15 years 2 months ago
Rotating Decode-and-Forward for Two Pairs of Two-Way Communications
We study the transmission strategy for a system consisting of two pairs of two-way communication links. The information exchange between the two nodes in each pair can only occur w...
Yiwei Pu, Cen Lin, Meixia Tao
ISSRE
2010
IEEE
15 years 2 months ago
Preventing Overflow Attacks by Memory Randomization
Buffer overflow is known to be a common memory vulnerability affecting software. It is exploited to gain various kinds of privilege escalation. C and C++ are very commonly used to ...
Vivek Iyer, Amit Kanitkar, Partha Dasgupta, Raghun...