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MICRO
2006
IEEE
113views Hardware» more  MICRO 2006»
15 years 4 months ago
Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers
We examine the ability of CMPs, due to their lower onchip communication latencies, to exploit data parallelism at inner-loop granularities similar to that commonly targeted by vec...
Jack Sampson, Rubén González, Jean-F...
ADT
2005
15 years 4 months ago
High rate compression of CAD meshes based on subdivision inversion
In this paper we present a new framework, based on subdivision surface approximation, for efficient compression and coding of 3D models represented by polygonal meshes. Our algorit...
Guillaume Lavoué, Florent Dupont, Atilla Ba...
ALGORITHMICA
2002
83views more  ALGORITHMICA 2002»
15 years 4 months ago
A Tutorial for Designing Flexible Geometric Algorithms
The implementation of an algorithm is faced with the issues efficiency, flexibility, and ease-of-use. In this paper, we suggest a design concept that greatly increases the flexibi...
Vikas Kapoor, Dietmar Kühl, Alexander Wolff
CORR
2002
Springer
83views Education» more  CORR 2002»
15 years 4 months ago
Optimal Ordered Problem Solver
We introduce a general and in a certain sense time-optimal way of solving one problem after another, efficiently searching the space of programs that compute solution candidates, i...
Jürgen Schmidhuber
MICRO
2000
IEEE
72views Hardware» more  MICRO 2000»
15 years 4 months ago
PipeRench implementation of the instruction path coprocessor
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
Yuan C. Chou, Pazhani Pillai, Herman Schmit, John ...