We examine the ability of CMPs, due to their lower onchip communication latencies, to exploit data parallelism at inner-loop granularities similar to that commonly targeted by vec...
In this paper we present a new framework, based on subdivision surface approximation, for efficient compression and coding of 3D models represented by polygonal meshes. Our algorit...
The implementation of an algorithm is faced with the issues efficiency, flexibility, and ease-of-use. In this paper, we suggest a design concept that greatly increases the flexibi...
We introduce a general and in a certain sense time-optimal way of solving one problem after another, efficiently searching the space of programs that compute solution candidates, i...
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
Yuan C. Chou, Pazhani Pillai, Herman Schmit, John ...