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DFT
2009
IEEE
189views VLSI» more  DFT 2009»
15 years 11 months ago
Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms
Pre-fabrication design verification and post-fabrication chip testing are two important stages in the product realization process. These two stages consume a large part of resourc...
Meng Zhang, Anita Lungu, Daniel J. Sorin
DFT
2009
IEEE
154views VLSI» more  DFT 2009»
15 years 11 months ago
Dual-Layer Cooperative Error Control for Reliable Nanoscale Networks-on-Chip
We propose a framework that allows dual-layer cooperative error control in a nanoscale network-on-chip (NoC), to simultaneously improve reliability, performance and energy efficie...
Qiaoyan Yu, Paul Ampadu
ICASSP
2009
IEEE
15 years 11 months ago
Independent component analysis for noisy speech recognition
Independent component analysis (ICA) is not only popular for blind source separation but also for unsupervised learning when the observations can be decomposed into some independe...
Hsin-Lung Hsieh, Jen-Tzung Chien, Koichi Shinoda, ...
ICSM
2009
IEEE
15 years 11 months ago
On the use of relevance feedback in IR-based concept location
Concept location is a critical activity during software evolution as it produces the location where a change is to start in response to a modification request, such as, a bug repo...
Gregory Gay, Sonia Haiduc, Andrian Marcus, Tim Men...
ICSEA
2008
IEEE
15 years 11 months ago
Model-Driven Development of Human Tasks for Workflows
In order to increase efficiency, enterprises support their business processes by information technology (IT). The majority of business processes requires human interaction. By mea...
Stefan Link, Philip Hoyer, Thomas Schuster, Sebast...