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» On equivalence checking and logic synthesis of circuits with...
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DAC
2000
ACM
14 years 7 months ago
Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization
In this paper, we propose a technique to implement communication protocols as hardware circuits using a model of concurrent EFSMs with multi-way synchronization. Since use of mult...
Hisaaki Katagiri, Keiichi Yasumoto, Akira Kitajima...
ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
13 years 10 months ago
Node Mergers in the Presence of Don't Cares
Abstract-- SAT sweeping is the process of merging two or more functionally equivalent nodes in a circuit by selecting one of them to represent all the other equivalent nodes. This ...
Stephen Plaza, Kai-Hui Chang, Igor L. Markov, Vale...
ICCAD
1996
IEEE
92views Hardware» more  ICCAD 1996»
13 years 10 months ago
Generation of BDDs from hardware algorithm descriptions
We propose a new method for generating BDDs from hardware algorithm descriptions written in a programming language. Our system can deal with control structures, such as conditiona...
Shin-ichi Minato
ISSTA
2004
ACM
13 years 11 months ago
Faster constraint solving with subtypes
Constraints in predicate or relational logic can be translated into boolean logic and solved with a SAT solver. For faster solving, it is common to exploit the typing of predicate...
Jonathan Edwards, Daniel Jackson, Emina Torlak, Vi...