14 search results - page 3 / 3 » On equivalence checking and logic synthesis of circuits with... |
DAC
2000
ACM
14 years 7 months ago
2000
ACM
In this paper, we propose a technique to implement communication protocols as hardware circuits using a model of concurrent EFSMs with multi-way synchronization. Since use of mult...
ASPDAC
2007
ACM
13 years 10 months ago
2007
ACM
Abstract-- SAT sweeping is the process of merging two or more functionally equivalent nodes in a circuit by selecting one of them to represent all the other equivalent nodes. This ...
ICCAD
1996
IEEE
13 years 10 months ago
1996
IEEE
We propose a new method for generating BDDs from hardware algorithm descriptions written in a programming language. Our system can deal with control structures, such as conditiona...
ISSTA
2004
ACM
13 years 11 months ago
2004
ACM
Constraints in predicate or relational logic can be translated into boolean logic and solved with a SAT solver. For faster solving, it is common to exploit the typing of predicate...