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» On formal models for social verification
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CODES
2008
IEEE
14 years 11 months ago
Model checking SystemC designs using timed automata
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
Paula Herber, Joachim Fellmuth, Sabine Glesner
CAV
2006
Springer
132views Hardware» more  CAV 2006»
15 years 1 months ago
Symmetry Reduction for Probabilistic Model Checking
We present an approach for applying symmetry reduction techniques to probabilistic model checking, a formal verification method for the quantitative analysis of systems with stocha...
Marta Z. Kwiatkowska, Gethin Norman, David Parker
DAC
2007
ACM
15 years 1 months ago
Memory Modeling in ESL-RTL Equivalence Checking
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence betwe...
Alfred Kölbl, Jerry R. Burch, Carl Pixley
SIGSOFT
2005
ACM
15 years 10 months ago
Online testing with model programs
Online testing is a technique in which test derivation from a model program and test execution are combined into a single algorithm. We describe a practical online testing algorit...
Margus Veanes, Colin Campbell, Wolfram Schulte, Ni...
63
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HPCA
2002
IEEE
15 years 10 months ago
Modeling Value Speculation
Several studies of speculative execution based on values have reported promising performance potential. However, virtually all microarchitectures in these studies were described i...
Yiannakis Sazeides