36 search results - page 5 / 8 » On generating compact test sequences for synchronous sequent... |
DSD
2005
IEEE
15 years 3 months ago
2005
IEEE
Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subta...
ITC
1989
IEEE
15 years 1 months ago
1989
IEEE
: The concept of a pseudo-exhaustive test for sequential circuits is introduced in a similar way as it is used for combinational networks. Instead of test sets one has to apply pse...
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VTS
1996
IEEE
15 years 1 months ago
1996
IEEE
A fault-oriented sequential circuit test generator is described in which various types of distinguishing sequences are derived, both statically and dynamically, to aid the test ge...
VTS
1998
IEEE
15 years 1 months ago
1998
IEEE
This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
Transparent-scan was proposed as an approach to test generation and test compaction for scan circuits. Its effectiveness was demonstrated earlier in reducing the test application ...