36 search results - page 6 / 8 » On generating compact test sequences for synchronous sequent... |
151
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VTS
2000
IEEE
15 years 10 months ago
2000
IEEE
We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence gen...
149
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TCAD
1998
15 years 5 months ago
1998
—New methods for fault-effect propagation and state justification that use finite-state-machine sequences are proposed for sequential circuit test generation. Distinguishing se...
202
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EVOW
1999
Springer
15 years 10 months ago
1999
Springer
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
155
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DAC
1995
ACM
15 years 9 months ago
1995
ACM
Abstract A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences t...
158
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VLSID
2007
IEEE
16 years 6 months ago
2007
IEEE
We introduce a novel method of test generation for microprocessors at the RTL using spectral methods. Test vectors are generated for RTL faults, which are the stuck-at faults on i...