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» On load latency in low-power caches
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ESTIMEDIA
2009
Springer
14 years 7 months ago
Inter-kernel data reuse and pipelining on chip-multiprocessors for multimedia applications
The increasing demand for low power and high performance multimedia embedded systems has motivated the need for effective solutions to satisfy application bandwidth and latency req...
Luis Angel D. Bathen, Yongjin Ahn, Nikil D. Dutt, ...
ISCC
2007
IEEE
100views Communications» more  ISCC 2007»
15 years 3 months ago
A Caching Algorithm using Evolutionary Game Theory in a File-Sharing System
In a P2P file-sharing system, a node finds and retrieves its desired file. If multiple nodes cache the same file to provide others, we can achieve a file-sharing system with ...
Masahiro Sasabe, Naoki Wakamiya, Masayuki Murata
MICRO
2006
IEEE
82views Hardware» more  MICRO 2006»
15 years 3 months ago
Yield-Aware Cache Architectures
One of the major issues faced by the semiconductor industry today is that of reducing chip yields. As the process technologies have scaled to smaller feature sizes, chip yields ha...
Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonath...
ISCA
1995
IEEE
120views Hardware» more  ISCA 1995»
15 years 1 months ago
Streamlining Data Cache Access with Fast Address Calculation
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
Todd M. Austin, Dionisios N. Pnevmatikatos, Gurind...
84
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IEEEPACT
1999
IEEE
15 years 1 months ago
Memory System Support for Image Processing
Image processing applications tend to access their data non-sequentially and reuse that data infrequently. As a result, they tend to perform poorly on conventional memory systems ...
Lixin Zhang, John B. Carter, Wilson C. Hsieh, Sall...